1. Field of the Invention
The present invention relates to a serial clock generator, and more specifically to a serial clock generating circuit for use in a serial data transfer circuit included in data processing systems including microcomputers, which serial clock generating circuit can comply with a case in which a level of a serial data transfer signal line changes in a predetermined period of time.
2. Description of Related Art
Conventionally, a serial data transfer circuit, which is one of various peripheral hardwares of data processing systems, has been widely used in comparison with a parallel data transfer circuit utilizing a bus connection, because the number of signal lines required for data transfer is small and therefore is economic, and because of other reasons.
On the other hand, data processing systems have been required to communicate with various peripheral devices and other data processing systems. However, a serial transfer rate or frequency being used is different dependently upon the devices and the systems coupled to the data processing system. Therefore, a serial data transfer circuit included in the data processing systems has been desired to easily deal with serial transfer frequencies of a wide extent, for example by a software processing with a central processing unit.
In a data transfer system for sending and receiving serial data, particularly, in a serial transfer system does not receive a serial clock for synchronizing receipt of the transfer data, a receiving side of the serial data transfer is required to have a circuit for generating a serial clock for receiving a transmitted data.
The serial clock generating circuit provided at the receiving side of the serial data transfer has been adapted to prepare an internal count clock having a frequency N times (for example, 16 times or 32 times) of a serial transfer rate which is previously determined between a sending side and the receiving side. The internal count clock is frequency-divided so as to generate an internal serial clock having the same period as that of the serial transfer rate. In addition, the generated receiving side serial clock is phase-adjusted to become in phase with a sending side serial clock signal, by changing a frequency division rate of the internal clock.
This phase-matching of the receiving side serial clock with the received serial data is ceaselessly performed at each signal level transition on a serial data transfer signal line. The reason for this is that even if the phase-matching has been realized at once, a phase-mismatching will occur between a serial clock of the sending side and a serial clock of the receiving side due to various causes such as a delay of a transfer path and a change of temperature of environment.
In brief, conventional serial clock generating circuits are basically constructed such that a clock generator generates an internal count clock, which is counted by an binary counter, so that a frequency divided clock is generated by the binary counter as an internal serial clock. A timing of clearing the binary counter is controlled or adjusted by detecting an edge or transition of the received serial data, so that the generated internal serial clock phase-adjusted to become in phase with the sending side serial clock signal. However, the binary counter has a fixed length, and therefore, if the internal count clock has a fixed frequency, the generated internal serial clock also have a fixed frequency.
Therefore, in case of requiring to realize a plurality of serial data transfers having different transfer frequencies by using the conventional serial clock generating circuit, one method is to provide a plurality of quartz-crystal oscillators and to select an appropriate one from the plurality of quartz-crystal oscillators by means of software processing so that a desired count clock is supplied to the serial clock generating circuit. However, the provision of the plurality of quartz-crystal oscillators will results in an increased number of parts in an application system, and hence, in an increased cost of the application system.
Another method is to use a frequency-division circuit which is provided independently of the serial clock generating circuit and which is connected to receive and frequency-divide a clock generated by a single quartz-crystal oscillator so as to supply a count clock having any selected frequency. In this case, since the frequency-dividing circuit is ordinarily composed of a binary counter, a quartz-crystal oscillator must be used which has an oscillation frequency as high as possible, in order to ensure that the serial clock generating circuit can generate a plurality of serial clocks having arbitrary different frequencies without decreasing a resolution of the serial clock generating circuit. However, it can ordinarily be said that the higher the oscillation frequency becomes, the more the quartz-crystal oscillator becomes expensive, and the larger the power consumption of the circuit becomes.
In addition, a modification is not so easy which makes it possible to change the bit length and the number of counts in a software manner. Furthermore, it is in some case that peripheral instruments and apparatuses coupled to the data processing system including therein the serial clock generating circuit are different in the magnitude or degree of minute change of the serial transfer frequency. In this case, it is required to change a modification value for eliminating a phase deviation between the received serial data and the receiving side serial clock, but it is not so easy.